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order number: 278875-005US may 2005 intel? 41210 serial to parallel pci bridge datasheet product features pci express specification , revision 1.0a support for single x8, single x4 or single x1 pci express operation. 64-bit addressing support 32-bit crc (cyclic redundancy checking) covering all transmitted data packets. 16-bit crc on all link message information. raw bit-rate on the data pins of 2.5 gbit/s, resulting in a raw bandwidth per pin of 250 mb/s. maximum realized bandwidth on pci express interface is 2 gb/s (in x8 mode) in each direction simultaneously, for an aggregate of 4 gb/s. pci local bus specification , revision 2.3. pci-to-pci bridge specification , revision 1.1. pci-x addendum to the pci local bus specification , revision 1.0b 64-bit 66 mhz, 3.3 v, not 5 v tolerant. on die termination (odt) with 8.3kohm pull-up to 3.3v for pci signals. six external req/gnt pairs for internal arbiter on segment a and b respectively. programmable bus parking on either the last agent or always on the 41210 bridge 2-level programmable round-robin internal arbiter with multi-transaction timer (mtt) external pci clock-feed support for asynchronous primary and secondary domain operation. 64-bit addressing for upstream and downstream transactions downstream lock# support. no upstream lock# support. pci fast back-to-back capable as target. up to four active and four pending upstream memory read transactions up to two downstream delayed (memory read, i/o read/write an d configuration read/ write) transaction. tunable inbound read prefetch algorithm for pci mrm/mrl commands device hiding support for secondary pci devices. secondary bus private memory support via opaque memory region local initialization via smbus secondary side initialization via type 0 configuration cycles. full peer-to-peer read/write capability between the two secondary pci segments.
2 information in this document is provided in connection with intel? products. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty relating to sale and/or use of intel products, including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. intel products are not intended for use in medical, life saving , life sustaining, critical control or safety systems, or in nuc lear facility applications. intel may make changes to specifications and product descriptions at any time, without notice. the intel? 41210 serial to parallel pci bridge may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . anypoint, appchoice, boardwatch, bunnypeople, cableport, celeron, chips, ct media, dialogic, dm3, etherexpress, etox, flashfile , i386, i486, i960, icomp, instantip, intel, intel centrino, intel logo, intel3 86, intel486, intel740, inteldx2, inteldx4, intelsx2, intel cr eate & share, intel gigablade, intel inbusiness, intel inside, intel inside logo, intel netburst, intel netmerge, inte l netstructure, intel play, intel play l ogo, intel singledriver, intel speedstep, intel strataflash, intel teamstation, intel xeon, in tel xscale, iplink, itanium, mcs, mmx, mmx logo, optimizer logo, overdrive, paragon, pc dads, pc parents, pdcharm, pentium, pentium ii xeon, pentium iii xeon, performance at your command, remoteexpress, smartdie, solutions960, sound mark, storageexpress, the computer inside., the journey inside, tokenexpress, voicebrick, vtune, and xircom are trademarks or registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation
3 contents contents 1 introduction ............................................................................................................................... ..... 7 1.1 about this document ......................................................................................................... .. 7 1.2 product overview ............................................................................................................ ..... 7 2 signal description ......................................................................................................................... 8 2.1 on die termination (odt).................................................................................................... 8 2.2 pci express interface....................................................................................................... ..10 2.3 pci bus interface (two instances) .....................................................................................10 2.4 pci bus interface 64-bit extension (two interfaces) .........................................................12 2.5 pci bus interface clocks and, reset and power management (two interfaces) ..............13 2.6 interrupt interface (two interfaces) ....................................................................................13 2.7 reset straps ................................................................................................................ .......13 2.8 smbus interface ............................................................................................................. ....15 2.9 miscellaneous pins .......................................................................................................... ...15 3 electrical and thermal characteristics .....................................................................................17 3.1 dc voltage and current specifications ..............................................................................17 3.2 ac specifications........................................................................................................... .....25 3.3 voltage filter specifications ............................................................................................... 27 3.4 vcc15 and vcc33 voltage requirements ........................................................................27 3.5 timing specifications ....................................................................................................... ...28 3.6 41210 bridge power consumption .....................................................................................36 3.7 power delivery guidelines..................................................................................................3 7 3.8 reference and compensation pins ....................................................................................37 3.9 thermal specifications ...................................................................................................... .38 4 package specification and ballout ............................................................................................40 4.1 package specification ....................................................................................................... .40 4.2 ball map .................................................................................................................... ..........42 4.3 signal list, sorted by ball location.....................................................................................44 4.4 signal list, sorted by signal name.....................................................................................48 figures 1 minimum transmitter timing and voltage output compliance specification.............................22 2 compliance test/measurement load.........................................................................................23 3 minimum receiver eye timing and voltage compliance specification .....................................23 4 voltage requirements vcc33 versus vcc15 ...........................................................................27 5 pci output timing ............................................................................................................. .........31 6 pci input timing .............................................................................................................. ...........31 7 pci-x 3.3v clock waveform ..................................................................................................... .33 8 41210 bridge reference and compensation circuit implementations .......................................38 9 41210 bridge package dimensions (top view) .........................................................................40 10 41210 bridge package dimensions (side view) ........................................................................41
4 contents tables 1 odt signals ................................................................................................................... .............. 9 2 pci express interface pins.................................................................................................... ..... 10 3 pci interface pins............................................................................................................ ........... 11 4 pci interface pins: 64-bit extensions......................................................................................... 12 5 pci clock and reset pins ...................................................................................................... .... 13 6 interrupt interface pins ...................................................................................................... ......... 13 7 reset strap pins.............................................................................................................. ........... 14 8 smbus interface pins .......................................................................................................... ....... 15 9 miscellaneous pins ............................................................................................................ ......... 15 10 intel? 41210 bridge dc voltage specifications ......................................................................... 17 11 dc characteristics input signal association .............................................................................. 18 12 dc input characteristics..................................................................................................... ........ 18 13 dc characteristic output signal association ............................................................................. 18 14 dc output characteristic..................................................................................................... ....... 19 15 differential transmitter (tx) dc output specifications .............................................................. 19 16 differential receiver (rx) dc input specifications .................................................................... 21 17 dc specifications for pci and pci-x 3.3 v signaling ................................................................ 24 18 dc specification for input clock signals .................................................................................... 2 5 19 dc specification for output clock signals ................................................................................. 25 20 conventional pci 3.3v ac characteristics ................................................................................ 25 21 pci-x 3.3v ac characteristics ................................................................................................ ... 26 22 differential transmitter (tx) ac output specifications .............................................................. 28 23 differential receiver (rx) ac input specifications..................................................................... 29 24 pci interface timing......................................................................................................... .......... 30 25 pci-x 3.3v signal timing parameters ....................................................................................... 31 26 pci and pci-x clock timings .................................................................................................. .. 33 27 41210 bridge clock timings................................................................................................... .... 35 28 41210 bridge maximum voltage plane currents ....................................................................... 37 29 41210 bridge thermal voltage plane currents .......................................................................... 37 30 41210 bridge thermal specifications ......................................................................................... 3 9 31 signal list, sorted by ball name............................................................................................. .... 44 32 signal list, sorted by signal name........................................................................................... .. 48
5 contents revision history date revision description may 2005 005 revised ta b l e 1 , table 9 , and section 3.8 april 2005 004 revised table 26 ?pci and pci-x clock timings? on page 33 clk cycle time parameters september 2004 003 revised first page pci express operation description; updated information in table 2. june 2004 002 added chapter 2. removed original sections 3.6 and 3.7. updated vcc information to vcc15. september 2003 001 initial release
order number: 278875-005US may 2005
datasheet ? 41210 bridge 7 introduction 1 1.1 about this document this document provides information on the intel ? 41210 serial to parallel pci bridge, including a functional overview, signal descriptions, mechan ical data, package signal location and bus functional waveforms. 1.2 product overview the intel? 41210 serial to parallel pci bridge (also called the 41210 bridge) integrates two pci express-to-pci/pci-x bridges. each bridge follows the pci-to-pci bridge programming model. the pci express port is compatible with the pci express specification , revision 1.0a. the two pci bus interfaces are compatible with the pci local bus specification , revision 2.3 and pci-x addendum to the pci local bus specification , revision 1.0b.
41210 bridge ? datasheet 8 signal description 2 the ?#? symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present after the signal name the signal is asserted when at the high voltage level. the fo llowing notations are used to describe the signal type: i: input pin o: output pin od: open-drain output pin i/o: bidirectional input/output pin i/od: bidirectional input/open-drain output pin 2.1 on die termination (odt) the 41210 bridge incorporates on-die terminati on for most of the pci interface signals. this eliminates the need for the system designer to incorporate external pull-up resistors in the design. the following signals have an on die termination of 8.33kohm @40%:
datasheet ? 41210 bridge 9 table 1. odt signals a_ack64# b_ack64# a_ad[63:32] b_ad[63:32] a_cbe#[7:4] b_cbe#[7:4] a_devsel# b_devsel# a_frame# b_frame# a_gnt#[5:0] b_gnt#[5:0] a_irdy# b_irdy# a_par b_par a_par64 b_par64 a_perr# b_perr# a_lock# b_lock# a_req#[5:0] b_req#[5:0] a_req64# b_req64# a_serr# b_serr# a_stop# b_stop# a_trdy# b_trdy# a_inta# b_inta# a_intb# b_intb# a_intc# b_intc# a_intd# b_intd# tck tdi tdo tms
41210 bridge ? datasheet 10 2.2 pci express interface table 2. pci express interface pins 2.3 pci bus interface (two instances) each interface is marked by either the letter ?a ? or ?b? to signify the interface. therefore, a_ad refers to the ad bus on pci bus a, and b_ad refers to the ad bus on pci bus b. for pin names described in the following sections, an ?x? in the name indicates either a or b, for the pci bus a and pci bus b sides. for example, x_par signal would be called a_par on the pci bus a and b_par on the pci bus b. signal i/o description refclkp/ refclkn i pci express reference clocks : 100 mhz differential clock pair. petp[7:0]/ petn[7:0] o pci express serial data transmit: pci express differential data transmit signals. x8 mode: all petp[7:0]/ petn[7:0] are used x4 mode: only petp[3:0]/ petn[3:0] are used x1 mode: either petp[0]/ petn[0] is used or petp[7]/ petn[7] is used perp[7:0]/ pern[7:0] i pci express serial data receive: pci express differential data receive signals. x8 mode: all perp[7:0]/ pern[7:0] are used x4 mode: only perp[3:0]/ pern[3:0] are used x1 mode: either perp[0]/ pern[0] is used or perp[7]/ pern[7] is used pe_rcomp[1:0] i pci express compensation inputs: analog signals. connect to a 24.9 ?1% pull-up resitor to 1.5v. a single resistor can be used for both signals. to ta l 3 6
datasheet ? 41210 bridge 11 table 3. pci interface pins (sheet 1 of 2) signal i/o description a_ad[31:0] b_ad[31:0] i/o pci address/data: these signals are a multiplexed address and data bus. during the address phase or phases of a transaction, the initiator dr ives a physical address on x_ad[31:0]. during the data phases of a transaction, the initiator drives write data, or the ta rget drives read data. no external pull-up resistors are r equired on the system board for these signals. a_c/be#[3:0] b_c/be#[3:0] i/o bus command and byte enables: these signals are a multiplexed command field and byte enable field. during the address phase or phases of a trans action, the initiator drives the transaction type on c/be#[3:0]. when there are two address phases, t he first address phase carries the dual address command and the second address phase carries the transaction type. for both read and write transactions, the initiator dr ives byte enables on c/be#[3:0] during the data phases. no external pull-up resistors are r equired on the system board for these signals. a_par b_par i/o parity: even parity calculated on 36 bits - ad[31:0] plus c/be[3:0]#. it is calculated on all 36 bits regardless of the valid byte enables. it is generated for address and data phases. it is driven identically to the ad[31:0] lines, except it is del ayed by exactly one pci clock. it is an output during the address phase for all 41210 bridge initiat ed transactions and all data phases when the 41210 bridge is the initiator of a pci write transaction, and when it is the target of a read transaction. 41210 bridge checks parity when it is the initiator of pci read transactions and when it is the target of pci write transactions. no external pull-up resistors are r equired on the system board for these signals. a_devsel# b_devsel# i/o device select: the bridge asserts devsel# to claim a pci transaction. as a target, the 41210 bridge asserts devsel# when a pci master peripheral attempts an access an address destined for pci express. as an initiator, devsel# indicates the response to a 41210 bridge initiated transaction on the pci bus. devsel# is tri-stated from the leading edge of pcirst#. devsel# remains tri-stated by the 41210 bridge until driven as a target. no external pull-up resistors are r equired on the system board for these signals. a_frame# b_frame# i/o frame: frame# is driven by the initiator to indicate the beginning and duration of an access. while frame# is asserted data transfers continue. when frame# is negated the transaction is in the final data phase. no external pull-up resistors are r equired on the system board for these signals. a_irdy# b_irdy# i/o initiator ready: irdy# indicates the ability of the initiator to complete the current data phase of the transaction. a data phase is completed when both irdy# and trdy# are sampled asserted. no external pull-up resistors are r equired on the system board for these signals. a_trdy# b_trdy# i/o target ready: indicates the ability of the target to complete the current data phase of the transaction. a data phase is completed when both trdy# and irdy# are sampled asserted. trdy# is tri-stated from the leading edge of rst#. trdy# remains tri-stated by the 41210 bridge until driven as a target. no external pull-up resistors are r equired on the system board for these signals. a_stop# b_stop# i/o stop: indicates that the target is requesting an initiator to stop the current transaction. no external pull-up resistors are r equired on the system board for these signals. a_perr# b_perr# i/o parity error: driven by an external pci device when it receives data that has a parity error. driven by 41210 bridge when, as a initiator it detects a parity error during a read transaction and as a target during write transactions. no external pull-up resistors are r equired on the system board for these signals. a_serr# b_serr# i system error: the 41210 bridge samples serr# as an input and conditionally forwards it to the pci express. no external pull-up resistors are r equired on the system board for these signals. a_m66en b_m66en i/od 66 mhz enable: this input signal from the pci bus indicates the speed of the pci bus. if it is high then the bus speed is 66 mhz and if it is low then the bus speed is 33 mhz. this signal will be used to generate appropriate clock (33 or 66 mhz) on the pci bus. use an approximately 8.2k ? resistor to pull to vcc33 or pull-down to ground.
41210 bridge ? datasheet 12 2.4 pci bus interface 64-bit extension (two interfaces) a_pcixcap b_pcixcap i pci-x capable: indicates whether all devices on t he pci bus are pci-x devices, so that the 41210 bridge can switch into pci-x mode. use an approximately 8.2k ? resistor to pull to vcc33. a_lock# b_lock# o pci lock: indicates an exclusive bus operation and may require multiple transactions to complete. this signal is an output from the bridge when it is initiating exclusive transactions on pci. lock# is ignored when pci masters are granted the bus. locked transaction do not propagate upstream. no external pull-up resistors are required on the system board for these signals. to t a l 11 8 table 4. pci interface pins: 64-bit extensions signal i/o description a_ad[63:32] b_ad[63:32] i/o pci address/data: these signals are a multiple xed address and data bus. this bus provides an additional 32 bits to the pci bus. during the data phas es of a transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target drives the upper 32 bits of 64-bit read data, when req64# and ack64# are both asserted. a_c/be#[7:4] b_c/be#[7:4] i/o bus command and byte enables upper 4 bits: these signals are a multiplexed command field and byte enable field. for both reads and write transacti ons, the initiator will drive byte enables for the ad[63:32] data bits on c/be7:4] during t he data phases when re q64# and ack64# are both asserted. a_par64 b_par64 i/o pci interface upper 32 bits parity: this carries the even parity of the 36 bits of ad[63:32] and c/ be#[7:4] for both address and data phases. a_req64# b_req64# i/o pci interface request 64-bit transfer: this is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. it has the same timing as frame#. when the 41210 bridge is the initiator, this signal is an output. when the 41210 bridge is the target this signal is an input. a_ack64# b_ack64# i/o pci interface acknowledge 64-bit transfer: this is asserted by the target only when req64# is asserted by the initiator, to indicate the target ability to transfer data using 64 bits. it has the same timing as devsel#. tota l 78 table 3. pci interface pins (sheet 2 of 2) signal i/o description
datasheet ? 41210 bridge 13 2.5 pci bus interface clocks and, reset and power management (two interfaces) 2.6 interrupt interface (two interfaces) this section lists the interrupt interface signals. there are two sets of interrupt signals for the standard inta:intd pci signals. 2.7 reset straps the following signals are used for static configuration. these signals are all sampled on the rising edge of perst#. table 5. pci clock and reset pins signal i/o description a_clko[6:0] b_clko[6:0] o pci clock output: 33/66/100/133 mhz clock for a pci device. x_clk[6] must be connected to the respective x_clkin input. for feeding the pci interface logic. unused clock outputs may be disabled via the ?offset 43: pclkc ? pci clock control? register and should be treated as no connects on the board. note: registers are listed in the intel? 41210 serial to parallel pci bridge developer?s manual. a_clkin b_clkin i pci clock in: this signal is pci clock feedback input. this pin should be connected to the corresponding x_clko[6] through a 22 ?1% series resistor. a_rst# b_rst# o pci reset: the bridge asserts rst# to reset devices that reside on the secondary pci bus. a_pme# b_pme# i pci power management event: pci bus power management event signal. this is a shared open drain input from all the pci cards on the correspo nding pci bus segment. this is a level sensitive signal that will be converted to a pme event on pci express. this pin does not have on-die 8.3k pull-up. this pull-up must be provided externally. to t a l 20 table 6. interrupt interface pins signal i/o description a_inta# a_intb# a_intc# a_intd# b_inta# b_intb# b_intc# b_intd# i interrupt request bus: the interrupt lines from pci interrupts inta#:intd# can be routed to these interrupt lines. refer to the intel? 41210 serial to parallel pci bridge design guide for more information on device numbering. to t a l 8
41210 bridge ? datasheet 14 table 7. reset strap pins signal i/o description a_133en b_133en i pci-x 133 mhz enable: this pin, when high, allows the pci-x segment to run at 133 mhz when x_pcixcap is sampled high. when low, the pci-x segment will only run at 100 mhz when x_pcixcap is sampled high. use an approximately 8.2k ? resistor to pull to vcc33 or pull-down to ground. a_strap[6:0 ] b_strap[6:0 ] i internal test modes: straps 6, 2:0 should be pulled low and straps 5:3 must be pulled high for normal operation. x_strap logic level 0?0? 1?0? 2?0? 3?1? 4?1? 5?1? 6?0? use approximately an 8.2k ? resistor to pull-up to vcc33 or pull-down to vss a_test[2:1] b_test{2:1] i internal test modes: these straps should be pulled high to vcc33. use approximately an 8.2k ? resistor to pull-up to vcc33. cfgretry i configuration retry: this pin, when sampled high sets the configuration cycle retry bit (bit 3) in the bridge initialization regist er at offset fc. if no local initialization is needed, this pin should be pulled low to vss. refer to the intel? 41210 serial to parallel pci bridge design guide for more information. to t a l 19
datasheet ? 41210 bridge 15 2.8 smbus interface table 8. smbus interface pins 2.9 miscellaneous pins table 9. miscellaneous pins signal i/o description smbclk i/od smbus clock: this signal should be pulled to 3.3v via an 8.2kohm resistor. smbdat i/od smbus data: this signal should be pulled to 3.3v via an 8.2kohm resistor. smbus[5] smbus[3:1] i smbus addressing straps: these straps set the smbus address for 41210 bridge. the address is determined as indicated below: bit 7?1? bit 6?1? bit 5smbus[5] bit 4?0? bit 3smbus[3] bit 2smbus[2] bit 1smbus[1] these signals (bits 5, 3:1) should be pulled up to 3.3v or down to ground. sampled at the rising edge of perst#. to t a l 6 signal i/o description cfgrst# o configuration reset: this signal is asserted low when ever the bridge goes through a fundemental reset (perst#, rstin#, or pci express reset). this signal should be used to indicate when the local initialization methods should be executed. refer to the intel? 41210 serial to parallel pci bridge design guide for more information. perst# i pci express fundamental reset: when low, asynchronously resets the internal logic (including sticky bits). rstin# i reset in: when asserted, this signal asynchronously resets the internal logic and asserts x_rst# output for both pci interfaces. this signal should be pulled high for adapter card usage. tck i tap clock in : this is the input clock to the jtag tap controller. acceptable frequency is 0-16mhz if not utilizing jtag, this signal can be left as a no connect. tdi i test data in: this is the serial data input to the jtag bscan shift register chain and to the jtag bscan control logic. this is latched in on the rising edge of tck. if not utilizing jtag, this signal can be left as a no connect. tdo o test data output: this is the serial data output from the jtag bscan logic if not utilizing jtag, this signal can be left as a no connect.
41210 bridge ? datasheet 16 tms i test mode select: this signal controls the tap controller state machine to move to different states and is sampled on the rising edge of tck. if not utilizing jtag, this signal can be left as a no connect. trst# i test reset in: this signal is used to asynchronously reset the jtag bscan logic. if not utilizing jtag, connect this signal to ground through a 1k ? pull-down resistor. reserved[8:1] i reserved: (8 pins) these input pins should be pulled low use an approximately 8.2k ? resistor to pull-down to ground. nc[19:18], nc[16:1] a_nc[10:1] b_nc[10:1] o no connect: (39 pins) these output pins should be left floating nc[17] o this signal requires an external pull-up, 8.2k ohm to 3.3v to t a l 57 signal i/o description
datasheet ? 41210 bridge 17 electrical and thermal characteristics 3 3.1 dc voltage and current specifications 3.1.1 41210 bridge dc specifications 1. transient tolerance 5 mv above 1 mhz at package pin under dc load conditions. 2. transient tolerance 10 mv above 1 mhz at package pin under dc load conditions. table 10. intel ? 41210 bridge dc voltage specifications symbol parameter min typ max unit notes vcc15 intel ? 41210 bridge core 1.425 1.5 1.575 v vcc15 pci-x i/o voltage 1.425 1.5 1.575 v vccape analog pci express voltage 1.455 1.5 1.545 v 1 vccapci[2:0] analog pci voltages 1.455 1.5 1.545 vccbgpe analog bandgap voltage 2.425 2.5 2.575 2 vccpe pci express interface voltage 1.46 1.5 1.55 v vcc33 pci bus interface voltage 3.0 3.3 3.6 v p tdp thermal design power 10.2 w
41210 bridge ? datasheet 18 3.1.2 input characteristic signal association 3.1.3 dc input characteristics 3.1.4 dc characteristic output signal association table 11. dc characteristics input signal association symbol signals v ih1 /v il1 interrupt signals : a_irq[15:0]#, b_irq[15:0]# pci signals: a_ad[63:0], b_ad[63:0], a_cbe[7:0]#, b_cbe[7:0]#, a_par, b_par, a_devsel#, b_devsel#, a_frame#, b_fr ame#, a_irdy#, b_irdy#, a_trdy#, b_trdy#, a_stop#, b_stop#, a_perr#, b_perr#, a_serr#, b_serr#, a_req[5:0]#, b_req[5:0]#, a_m66en, b_m66en, a_133en, b_133en, a_pcixcap, b_pcixcap, a_par64, b_par64, a_req64#, b_req64#, a_ack64#, b_ack64# clock signals (3.3 v only): a_clki, b_clki miscellaneous signals: perst# v ih2 /v il2 pci express signals : refclk, refclk#, petp[7:0], petn[7:0], pe_rcomp[1:0] v ih3 /v il3 smb signals: smbdat, smbclk table 12. dc input characteristics symbol parameter 3.3 v signal unit min max v il1 input low voltage -0.5 0.35 vcc33 v v ih1 input high voltage 0.5 vcc33 vcc33 +0.5 v symbol parameter max v il2 input low voltage n/a v v ih2 input high voltage n/a v v il3 input low voltage 0.6 v v ih3 input high voltage vcc33 + 0.5 v table 13. dc characteristic output signal association symbol signals v oh1 /v ol1 pci signals : a_ad[63:0], b_ad[63:0], a_cbe[7:0]#, b_cbe[7:0]#, a_par, b_par, a_devsel#, b_devsel#, a_frame#, b_fr ame#, a_irdy#, b_irdy#, a_trdy#, b_trdy#, a_stop#, b_stop#, a_perr#, b_perr#, a_m66en, b_m66en, a_gnt[6:0]#, b_gnt[5:0]#, a_lock#, b_lock#, a_par64, b_par64, a_req64#, b_req64#, a_ack64#, b_ack64# pci clock signals (3.3 v only): a_clko[6:0], b_clko [6:0], a_rst#, b_rst# miscellaneous signals : raserr# v oh2 /v ol2 pci express signals: perp[7:0], pern[7:0] v oh3 /v ol3 smbus signals: smbdat, smbclk
datasheet ? 41210 bridge 19 3.1.5 dc output characteristics 3.1.6 pci express interface dc specifications 3.1.6.1 differential transmitter (tx) dc output specifications table 15 defines the dc specifications of parameters for the differential output at all transmitters (txs). the parameters are specified at the component pins. table 14. dc output characteristic symbol parameter 3.3 v signal unit notes min max v ol1 output low voltage 0.1vcc33 v (5 v) iout = 6 ma (3.3 v) iout = 1500 ua v oh1 output high voltage 0.9vcc33 v (5 v) iout = -2 ma (3.3 v) iout = -500 ua symbol parameter max unit notes v ol2 output low voltage n/a v v oh2 output high voltage n/a v v ol3 output low voltage 0.4 v i ol4 =14 ma v oh3 output high voltage n/a v open drain table 15. differential transmitter (tx) dc output specifications (sheet 1 of 2) symbol parameter min nom max units comments v tx-diffp-p differential peak to peak output voltage 0.80 1.2 v v tx-diffp-p = 2*|v tx-d+- v tx-d- | see note 1. v tx-de-ratio de-emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db this is the ratio of the v tx-diffp-p of the second and following bits after a transition divided by the v tx-diffp-p of the first bit after a transition see note 1. v tx-cm-acp ac peak common mode output voltage 20 mv v tx-cm-acp = |v tx-d+ + v tx-d- | / 2 ? v tx- cm-dc v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d-| / 2 during l0 see note 1. v tx-cm-dc- active-idle- delta absolute delta of dc common mode voltage during l0 and electrical idle 0 100 mv |v tx-cm-dc [during l0] ? v tx-cm-idle- dc[during electrical idle] | <= 100mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- | / 2 [electrical idle] see note 1.
41210 bridge ? datasheet 20 1. specified at the measurement point into a timing and voltage compliance test load as shown in figure 2, ?compliance test/measurement load? on page 23 and measured over any 250 c onsecutive tx uis. (also refer to the transmitter compliance eye diagram as shown in minimum transmitter timing and voltage output compliance specification.) 2. the transmitter input impedance shall result in a differential return loss greater than or equal to 12 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50w to ground for both the d+ and d- li ne (i.e., as measured by a vector network analyzer with 50w probes ? see figure 2 ). note that the series capacitors ctx is optional for the return loss measurement. v tx-cm-dc- line-delta absolute delta of dc common mode voltage between d+ and d-. 025mv |v tx-cm-dc-d+ [during l0] ? v tx-cm-dc-d- [during l0.] |<=25mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | [during l0] v tx-cm-dc-d- = dc (avg) of |v tx-d- | [during l0] see note 1. v tx-idle- diffp electrical idle differential peak output voltage 020mv v tx-idle-diffp = |v tx-idle-d+ - v tx-idle-d- |<=20mv see note 1. v tx-rcv- detect the amount of voltage change allowed during receiver detection. 600 mv the total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. rl tx-diff differential return loss 12 db measured over 50 mhz to 1.25 ghz see note 2. rl tx-cm common mode return loss 6db measured over 50 mhz to 1.25 ghz see note 2. z tx-diff-dc dc differential tx impedance 80 100 120 w tx dc differential mode low impedance z tx-com- high- imp-dc transmitter common mode high impedance state (dc) 5 k 20k w tx dc high impedance. c tx ac coupling capacitor 75 200 nf all transmitters shall be ac coupled. the ac coupling is required either within the media or within the transmitting component itself. table 15. differential transmitter (tx) dc output specifications (sheet 2 of 2)
datasheet ? 41210 bridge 21 3.1.6.2 differential receiver (rx) dc input specifications table 16 defines the dc specifications of parameters for all differential receivers (rxs). the parameters are specified at the component pins. 1. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 2, ?compliance test/measurement load? on page 23 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram as shown in figure 3, ?minimum receiver eye timing and voltage compliance specification? on page 23 ). if the clocks to the rx and tx are not derived from the same clock chip the tx ui must be used as a reference for the eye diagram. 2. the receiver input impedance shall result in a differential return loss greater than or equal to 15 db and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid in put levels. the reference impedance for return loss measurements for is 50 ? to ground for both the d+ and d- line (i.e., as measured by a vector network analyzer with 50 ? probes - see figure 2 ). note: that the series capacitors c tx is optional for the return loss measurement. 3. impedance during all operating conditions. 4. the rx dc common mode impedance that must be present when the receiver terminations are first enabled to ensure that the receiver detect occurs properly. compensation of this impedance can start immediately and the (z rx-com-dc )rxdc common mode impedance must be with in the specified range by the time detect is entered. 5. the rx dc common mode impedance that exists when the receiver terminations are disabled or when no power is present. this helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. table 16. differential receiver (rx) dc input specifications symbol parameter min nom max units comments v rx-diffp-p differential input peak to peak voltage 0.17 5 1.20 0 v v rx-diffp-p = 2*|v rx-d+ - v rx-d- | see note 1. v rx-cm-acp ac peak common mode input voltage 150 mv v rx-cm-ac = |v rx-d+ + vrx-d- |/2? v rx-cm-dc v rx-cm-dc = dc (avg) of |v rx-d+ +v rx-d- |/2 during l0 see note 1. rl rx-diff differential return loss 15 db measured over 50 mhz to 1.25 ghz see note 2. rl rx-cm common mode return loss 6db measured over 50 mhz to 1.25 ghz see note 2 z rx-diff-dc dc differential input impedance 80 100 120 w rx dc differential mode impedance. see note 3. z rx-com- dc dc input common mode input impedance 40 50 60 w rx dc common mode impedance 50 ?+/-20% tolerance. see notes 1 and 3. z rx-com- initial-dc initial dc input common mode input impedance 55060w rx dc common mode impedance allowed when the receiver terminations are first powered on. see note 4. z rx-com- high-imp- dc powered down dc input common mode input impedance 200 k w rx dc common mode impedance when the receiver terminations are not powered (i.e., no power). see note 5. v rx-idle- det-diffp- p electrical idle detect threshold 65 175 mv v rx-idle-det-diffp-p =2*|v rx-d+ - vrx-d- | measured at the package pins of the receiver.
41210 bridge ? datasheet 22 there are two eye diagrams that must be met fo r the transmitter. both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. the different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. the eye diagram must be valid for any 250 consecu tive uis. an appropriate average tx ui must be used as the interval fo r measuring the eye diagram. 3.1.6.3 compliance test and measurement load the ac timing and voltage parameters must be ve rified at the measurement point, as specified by the device vendor within 0.2 inches of the pack age pins, into a test/measurement load shown in figure 2 . note: the allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that package/board routing may benefit from d+ and d- not being exactly matched in length at the package pin boundary. if the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to be the d+ and d-package pins. figure 1. minimum transmitter timing and voltage output compliance specification
datasheet ? 41210 bridge 23 the test load is shown at the transmitter packag e reference plane, but the same test/measurement load is applicable to the receiver package reference plane. ctx is an optional portion of the measurement test load. the meas urement should be taken on the opposite side of the capacitor from the package, and the value of the ctx must be in the range of 75 nf to 200 nf. . the rx eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. the eye diagram must be valid for any 250 consecutive uis. an appropriate average tx ui must be used as the interval for measuring the eye diagram. figure 2. compliance test/measurement load figure 3. minimum receiver eye timing and voltage compliance specification
41210 bridge ? datasheet 24 3.1.6.4 pci and pci-x interface dc specifications table 17 summarizes the dc specifications for 3.3v signaling. 1. this specification should be guarant eed by design. it is the minimum voltage to which pull-up resistors are calculated to pull a floated network. app lications sensitive to static power utilization must assure that the input buffer is conducting minimum current at this input voltage. 2. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 3. absolute maximum pin capacitance for a pci/pcix input except x_clkin and x_idsel. 4. for conventional pci only, lower capacitance on this input-only pin allows for non-resistive coupling to x_ad[xx]. pci-x configuration transactions drive the ad bus four clocks before x_frame# asserts (see section 2.7.2.1, ?configuration transaction timing,? in the pci-x protocol addendum to the pci local bus specification revision 2.0a ). 5. for conventional pci, this is a recommendation, not an absolute requirement. for pci-x, this is a requirement. 6. this input leakage is the maximum allowable leakage into the x_pme# open drain driver when power is removed from vcc33 of the component. this assumes that no event has occurred to cause the device to attempt to assert x_pme#. table 17. dc specifications for pci and pci-x 3.3 v signaling symbol parameter min max units condition notes vcc33 supply voltage 3.0 3.6 v v ih input high voltage 0.5 vcc33 vcc33 +0.5 v v il input low voltage -0.5 0.3vcc33 v v ipu input pull-up voltage 0.7vcc33 v 1 i il input leakage current 10 a0 < v in < vcc33 2 v oh output high voltage 0.9vcc33 v i out = -500 a v ol output low voltage 0.1vcc33 v i out = 1500 a c in input pin capacitance 10 pf 3 c clk x_clkin pin capacitance 5 8 pf c idsel idsel pin capacitance 8 pf 4 l pin pin inductance 20 nh 5 i off x_pme# input leakage - 1 a v o 3.6 vcc33 off or floating 6
datasheet ? 41210 bridge 25 3.1.6.5 input clock dc specifications 3.1.6.6 output clock dc specifications 3.2 ac specifications 3.2.1 pci and pci-x ac characteristics table 18. dc specification for input clock signals symbol parameter min max units clk100 input low voltage -0.5 0.8 v clk100 input high voltage 2.0 vcc3.3 + 0.5 v clk133 input low voltage -0.5 0.8 v clk133 input high voltage 2.0 vcc3.3 + 0.5 v table 19. dc specification for output clock signals symbol parameter min max units condition clk33 output low voltage 0.4 v iol = 1 ma clk33 output high voltage 2.4 v ioh= -1 ma clk66 output low voltage 0.4 v iol = 1 ma clk66 output high voltage 2.4 v ioh= -1 ma clk100 output low voltage 0.4 v iol = 1 ma clk100 output high voltage 2.4 v ioh= -1 ma clk133 output low voltage 0.4 v iol = 1 ma clk133 output high voltage 2.4 v ioh= -1 ma table 20. conventional pci 3.3v ac characteristics (sheet 1 of 2) sym parameter condition min max unit note i oh(ac) switching current high v out = 0.7vcc33 -32vcc33 ma v out = 0.3vcc33 -12vcc33 ma 1 i ol(ac) switching current low v out = 0.18vcc33 38vcc33 ma v out = 0.6vcc33 16vcc33 ma 1 i ch high clamp current vcc33 + 4 > v in vcc33 + 1 25 + (v in ? vcc33 ? 1) / 0.015 ma
41210 bridge ? datasheet 26 1. in conventional pci switching, current characteristics for x_req# and x_gnt# are permitted to be one half of that specified here; i.e., half size drivers may be used on these signals. this specification does not apply to clk and rstin# which are system outputs. ?switching cu rrent high? specifications are not relevant to x_serr# which is an open drain output. 2. this parameter is to be interpreted as the cumulati ve edge rate across the specified range rather than the instantaneous rate at any point within the transition range. for more details on slew rate measurement conditions please refer to the pci-x electrical and mechanical addendum to the pci local bus specification, revision 2.0a 1. in conventional pci switching, current characteristics for x_req# and x_gnt# are permitted to be one half of that specified here; i.e., half size drivers may be used on these signals. this specification does not apply to clk and rst# which are system outputs. ?switching cu rrent high? specifications are not relevant to x_serr#, which is an open drain output. i cl low clamp current -3 < v in -1 -25 + (v in + 1) / 0.015 ma slew r output rise slew rate 0.3vcc33 to 0.6vcc33 14v/ns2 slew f output fall slew rate 0.6vcc33 to 0.3vcc33 14v/ns 2 table 20. conventional pci 3.3v ac characteristics (sheet 2 of 2) table 21. pci-x 3.3v ac characteristics sym parameter condition min max unit note i oh(ac) switching current high 0 < vcc33 ? v out 3.6v -74(vcc33 - v out ) ma 0 < vcc33 ? v out 1.2v -32 (vcc33 ? v out ) ma 1 1.2v < vcc33 ? v out 1.9v -11 (vcc33 - v out ) ? 25.2 ma 1 1.9v < vcc33 ? v out 3.6v -1.8 (vcc33 - v out ) ? 42.7 ma 1 i ol(ac) switching current low 0 v out 3.6v 100v out ma 0 < v out 1.3v 48v out 1 1.3v < v out 3.6v 5.7v out + 55 1 i cl low clamp current -3v < v in - 0.8875v -40 + (v in + 1) / 0.005 ma -0.8875v < v in -0.625v -25 + (v in + 1) / 0.015 ma i ch high clamp current 0.8875v < v in ? vcc33 -4v 40 + (v in ? vcc33 - 1) / 0.005 ma 0.625v < v in ? vcc33 0.8875v 25 + (v in ? vcc33 - 1) / 0.015 ma slew r output rise slew rate 0.3vcc33 to 0.6vcc33 14v/ns2 slew f output fall slew rate 0.6vcc33 to 0.3vcc33 14v/ns2
datasheet ? 41210 bridge 27 2. this parameter is to be interpreted as the cumulative edge rate across the specified range rather than the instantaneous rate at any point within the transition range. for more details on slew rate measurement conditions please refer to the pci-x electrical and mechanical addendum to the pci local bus specification, revision 2.0a . 3.3 voltage filter specifications the 41210 bridge requires voltage filtering to reduce noise on critical voltage planes. there are two filter types necessary on the platform: ? analog voltage filter (pci-express and pci) ? bandgap filter note: for filter specifications, refer to the 41210 serial to parallel pci bridge design guide. 3.4 vcc15 and vcc33 voltage requirements the 41210 bridge requires that the vcc33 voltage rail be equal to or no less than 0.5v below vcc15 (absolute voltage value) at all times during 41210 bridge operation, including during system power up and power down. in other words, the following must always be true: vcc33 (vcc15 ?0.5v) figure 4 graphically illustrates this requirement. this can be accomplished by placing a diode (with a voltage drop < 0.5v) between vcc15 and vcc33. anode will be connected to vcc15 and cathode will be connected to vcc33. figure 4. voltage requirements vcc33 versus vcc15
41210 bridge ? datasheet 28 3.5 timing specifications 3.5.1 pci express interface timing 3.5.1.1 differential transmitter (tx) ac output specifications table 22 defines the ac specifications of parameters for the differential output at all transmitters (txs). the parameters are specified at the component pins. 1. no test load is necessarily associated with this value. 2. specified at the measurement point into a timing and voltage compliance test load as shown in figure 2, ?compliance test/measurement load? on page 23 and measured over any 250 c onsecutive tx uis. (also refer to the transmitter compliance eye diagram as shown in minimum transmitter timing and voltage output compliance specification.) 3. a t tx-eye = 0.70 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.30 ui for the transmitter collected ov er any 250 consecutive tx uis. the t tx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total tx jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. table 22. differential transmitter (tx) ac output specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps each ui is 400 ps +/-300 ppm. ui does not account for ssc dictated variations. see note 1. t tx-eye minimum tx eye width 0.70 ui the maximum transmitter jitter can be derived as t tx-max-jitter = 1 - t tx-eye = .3 ui see notes 2 and 3. t tx-eye- median-to- max-jitter maximum time between the jitter median and maximum deviation for the median 0.15 ui jitter is defined as the measurement variation of the crossing points (v tx-diffp-p = 0v) in relation to an appropriate average tx ui. see notes 2 and 3. t tx-rise, t tx-fall d+/d- tx output rise/fall time 0.125 ui see notes 2 and 4. t tx-idle- min minimum time spent in electrical idle 50 ui minimum time a transmitter must be in electrical idle. t tx-idle- set- to-idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered-set 20 ui after sending an electrical idle ordered-set, the transmitter must meet all electrical idle specifications within this time. t tx-idle- rcv- detect- max maximum time spent in electrical idle before initiating a receiver detect sequence. 100 ms maximum time spent in electrical idle before initiating a receiver detect sequence. l tx-skew lane-to-lane output skew 500 ps between any two lanes within a single transmitter.
datasheet ? 41210 bridge 29 4. measured between 20-80% at transmitter pa ckage pins into a test load as shown in figure 2 for both v tx-d+ and v tx-d-. 3.5.1.2 differential receiver (rx) ac input specifications table 23 defines the ac specifications of parameters for all differential receivers (rxs). the parameters are specified at the component pins. 1. no test load is necessarily associated with this value. 2. specified at the measurement point and measured over any 250 consecutive uis. the test load in figure 2, ?compliance test/measurement load? on page 23 should be used as the rx device when taking measurements (also refer to the receiver compliance eye diagram as shown in figure 3, ?minimum receiver eye timing and voltage compliance specification? on page 23 ). if the clocks to the rx and tx are not derived from the same clock chip the tx ui must be used as a reference for the eye diagram. 3. a t rx-eye = 0.40 ui provides for a total sum of 0.60 ui deterministic and random jitter budget for the transmitter and interconnect collect ed any 250 consecutive uis. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which th e median and the maximum deviation from the median is less than half of the total .6 ui jitter budget collected over any 250 consecutive tx uis. it should be noted that the median is not the same as the mean. the jitter medi an describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. if the clocks to the rx and tx are not derived from the same clock chip , the appropriate average tx ui must be used as the reference for the eye diagram. table 23. differential receiver (rx) ac input specifications symbol parameter min nom max units comments ui unit interval 399.88 400 400.12 ps the ui is 400 ps +/-300 ppm. ui does not account for ssc dictated variations. see note 1. t rx-eye minimum receiver eye width 0.4 ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived ast rx-max-jitter =1 -t rx- eye =0.6 ui see notes 2 and 3. t rx-eye- median-to- max-jitter maximum time between the jitter median and maximum deviation from the median. 0.3 ui jitter is defined as the measurement variation of the crossing points (v rx- diffp-p = 0 v) in relation to an appropriate average tx ui. see notes 2 and 3. t rx-idle-det- diff- entertime unexpected electrical idle enter detect threshold integration time 10 ms an unexpected electrical idle (v rx- diffp-p 41210 bridge ? datasheet 30 3.5.2 pci and pci-x interface timing 1. it is important that all driven si gnal transitions drive to their v oh or v ol level within one t cyc . 2. minimum times are measured at the package pin (not the test point) with the load circuit shown in the pci-x electrical and mechanical addendum, revision 2.0a. maximum times are measured with the test point and load circuit shown in the pci-x electrical and mechanical addendum, revision 2.0a. 3. x_req_[5:0]# and x_gnt_[5:0]# are point-to-point signals and have different input setup times than do bused signals. x_gnt_[5:0]# and x_req_[5:0]# have a setup of 5 ns at 66 mhz. all other signals are bused. 4. see section 3.5, ?timing specifications? on page 28 and the measurement conditions in the pci-x electrical and mechanical addendum, revision 2.0a. 5. if x_m66en is asserted, clk is stable when it meets the requirements in the pci local bus specification revision 2.3 . rstin# is asserted and deasserted as ynchronously with respect to clk. 6. when x_m66en is asserted, the minimum specification for t val (min), t val (ptp)(min), and t on may be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when x_m66en is deasserted. 7. for purposes of active/float timing measurements, t he hi-z or ?off? state is defined to be when the total current delivered through the component pin is less t han or equal to the leakage current specification. 8. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. refer to the pci local bus specification revision 2.3 for more details. 9. maximum value is also limited by delay to the first transaction (t rhff ). table 24. pci interface timing functional operating range (vcc33 = 3.3 v + 5%, tcase=0 c to 105 c) 66 mhz 33 mhz symbol parameter min max min max units notes t val clk to signal valid delay; bused signals 2 6 2 11 ns 1, 2, 3 t val (ptp) clk to signal valid delay; point-to-point signals 2 6 2 12 ns 1, 2, 3 t on float to active delay 2 2 ns 1, 7 t off active to float delay 14 28 ns 1, 7 t su input setup time to clk; bused signals 3 7 ns 3, 4, 8 t su (ptp) input setup time to clk; point-to-point 5 10,12 ns 3, 4 t h input hold time from clk 0 0 ns 4 t rst reset active time after power stable 11ms5 t rst-clk reset active time after clk stable 100 100 s5 t rst-off reset active to output float delay 40 40 ns 5, 6 t rrsu pxreq64# to rstin# setup time 10 10 clocks t rrh rstin# to pxreq64# hold time 0 50 0 50 ns 9 t rhfa rstin# high to first configuration access 2 25 2 25 clocks t rhff rstin# high to first pxframe# assertion 55clocks t pvrh power valid to rstin# high 100 100 ms
datasheet ? 41210 bridge 31 figure 5. pci output timing figure 6. pci input timing table 25. pci-x 3.3v signal timing parameters (sheet 1 of 2) sym parameter pci-x 133 pci-x 66 units notes min max min max t val clk to signal valid delay 0.7 3.8 0.7 3.8 ns 1, 2, 8
41210 bridge ? datasheet 32 1. see the timing measurement conditions in section 3.5, ?timing specifications? on page 28 . 2. minimum times are measured at the package pin (not the test point) with the load circuit shown in the pci-x electrical and mechanical addendum, revision 2.0a. maximum times are measured with the test point and load circuit shown in pci-x electrical and mechanical addendum, revision 2.0a. 3. see the timing measurement conditions in section 3.5, ?timing specifications? on page 28 and the pci-x electrical and mechanical addendum, revision 2.0a. 4. rst# is asserted and deasserted asynchronously with respect to clk. 5. for purposes of active/float timing measurements, th e hi-z or "off" state is defined to be when the total current delivered through the component pin is less t han or equal to the leakage current specification 6. setup time applies only when the device is not driving the pin. devices cannot drive and receive signals at the same time. 7. maximum value is also limited by delay to the first transaction (t rhfa ). the pci-x initialization pattern control signals after the rising edge of rstin# must be deasserted no later than two clocks before the first pxframe# and must be floated no later than one clock before pxframe# is asserted. 8. device must meet this specification independent of how many outputs switch simultaneously. t on float to active delay 0 0 ns 1, 6, 8 t off active to float delay 7 7 ns 1, 6, 8 t su input setup time to clk 1.2 1.7 ns 3, 7 t h input hold time from clk 0.5 0.5 ns 3 t rst reset active time after power stable 11ms4 t rst-clk reset active time after clk stable 100 100 s4 t rst-off reset active to output float delay 40 40 ns 4 t rrsu pxreq64# to rstin# setup time 10 10 ns t rrh rstin# to pxreq64# hold time 0 50 0 50 ns 7 t rhfa rstin# high to first configuration access 2 26 2 26 clocks t rhff rstin# high to first pxframe# assertion 55clocks t pvrh power valid to rstin# high 100 100 ms t prsu pci-x initialization pattern to rstin# setup time 10 10 clocks t prh rstin# to pci-x initialization pattern hold time 0 50 0 50 ns 7 t rlcx delay from rstin# low to clk frequency change 00ns table 25. pci-x 3.3v signal timing parameters (sheet 2 of 2)
datasheet ? 41210 bridge 33 3.5.3 pci and pci-x clock specification clock measurement conditions are the same for pci-x devices as for conventional pci devices in a 3.3v signaling environment except for voltage levels specified in table 26, ?pci and pci-x clock timings? on page 33 . the same spread-spectrum clocking t echniques are allowed in pci-x as for 66 mhz conventional pci. if a device includes a p ll, that pll must track the input variations of spread-spectrum clocking specified in table 26 . 1. for clock frequencies above 33 mhz, the clock frequency may not change beyond the spread-spectrum and jitter limits except while rstin# is asserted. 2. this slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in the pci-x electrical and mechanical addendum, revision 2.0a. 3. the minimum clock period must not be violated for any si ngle clock cycle (i.e. accounting for all system jitter). 4. average t cyc is measured over any 1 s period of time and must include all sources of clock variation. figure 7. pci-x 3.3v clock waveform table 26. pci and pci-x clock timings symbol parameter pci-x 133 pci-x 66 pci 66 pci 33 min max min max min max min max units notes t cyc clk cycle time average 7.5 20 15 20 15 30 30 ns 1,3,4 absolute minimum 7.375 14.8 14.8 29.7 ns 1,3 t high clk high time 36611ns t low clk low time 36611ns t jit clk period jitter 125 -125 200 -200 200 -200 300 -300 ps 5 slew rate ? clk slew rate 1.5 4 1.5 4 1.5 4 1 4 v/ns 2 spread spectrum requirements fmod modulation frequency 30 33 30 33 30 33 khz fsprea d frequency spread -1 0 -1 0 -1 0 %
41210 bridge ? datasheet 34 5. period jitter is the deviation between any single period of the clock, t cyc , and the average period of the clock, t cyc(average) .
datasheet ? 41210 bridge 35 3.5.4 41210 bridge clock timings 1. period, jitter, offset and skew measured on rising edge @ 1.5v for 3.3v clocks. table 27. 41210 bridge clock timings symbol parameter min max units notes clk100 t period average period 10.0 10.2 ns 6 t rise rise time across 600 mv 300 600 ps 7,8 t fall fall time across 600 mv 300 600 ps 7,8 ? rise/fall matching 20% 7,9 ? cross point at 1 v 0.51 0.76 v t ccjitter cycle to cycle jitter 200 ps ?duty cycle4555% ? maximum voltage allowed at input 1.45 v ? minimum voltage allowed at input -200 mv ? rising edge ringback 0.85 v ? falling edge ring back 0.35 v clk133 t period average period 7.5 7.65 ns 6 t rise rise time across 600 mv 300 600 ps 7,8 t fall fall time across 600 mv 300 600 ps 7,8 ? rise/fall matching 20% 7,9 ? cross point at 1v 0.51 0.76 v t ccjitter cycle to cycle jitter 125 ps 10 ?duty cycle 45 55% ? maximum voltage allowed at input 1.45 v ? minimum voltage allowed at input -200 mv ? rising edge ringback 0.85 v ? falling edge ring back 0.35 v clk33 t period clk period 30.0 n/a ns 1,2 t high clk high time 12.0 n/a ns 3 t low clk low time 12.0 n/a ns 4 ? rising edge rate 1.0 4.0 v/ns 5 ? falling edge rate 1.0 4.0 v/ns 5 t rise clk rise time 0.5 2.0 ns 5 t fall clk fall time 0.5 2.0 ns 5
41210 bridge ? datasheet 36 2. the average period over any 1 us period of time must be gr eater than the minimum specified period. 3. t high is measured at 2.4v for non-host outputs. 4. t low is measured at 0.4v for all outputs. 5. for 3.3v clocks t rise and t fall are measured as a transition through the threshold region v ol = 0.4v and v oh = 2.4v (1 ma) jedec specification. 6. measured at crossing point. 7. measured from v ol = 0.2v to v oh = 0.8v. 8. still simulating to determine [0.2?0.8 v] or [0.3?0.9 v]. 9. determined as a fraction of 2*(t rise ? t fall ) / (t rise + t fall ). 10.period jitter is the deviation between any single period of the clock, t cyc , and the average period of the clock, t cyc (average). 3.5.4.1 spread spectrum clocking spread spectrum clocking can be used on the 41 210 bridge to reduce energy. spread spectrum clocking is a common technique used by system designers to meet fcc emissions, where the frequency is deliberately shifted around to spread th e energy off of the peak. the following is to be observed when using spread spectrum clocking: ? all device timings (including jitter, skew, min/max clock period, output rise/fall time) must meet the existing non-spread spectrum specifications ? all non-spread host and pci functionality must be maintained in the spread spectrum mode (includes all power management functions.) ? the minimum clock period cannot be violated. the preferred method is to adjust the spread technique to not allow for modulation above th e nominal frequency. this technique is often called ?down-spreading?. the modulation profile in a modulation period can be expressed as: equations: where: f nom is the nominal frequency in the non-ssc mode f m is the modulation frequency f m is the modulation amount t is time. 3.6 41210 bridge power consumption table 28 provides details on the maximum draw from the power planes by the 41210 bridge for use in voltage regulation. ? ? ? ? ? ? ? < < ? ? ? ? + < < ? ? ? + ? = , ) ( ; ) ( m m nom m nom m nom m nom f 1 t f 2 1 when t f f 2 f 1 f 2 1 t 0 when t f f 2 f 1 f
datasheet ? 41210 bridge 37 table 28. 41210 bridge maximum voltage plane currents table 29 provides details on the maximum nominal draw from the power planes by the 41210 bridge for use in thermal design. table 29. 41210 bridge thermal voltage plane currents 3.7 power delivery guidelines please refer to the intel? 41210 serial to parallel pci bridge design guide . 3.8 reference and compensation pins the 41210 bridge has one reference pin and three compensation pins: ? pe_rcomp[1:0] are two separate pins that provide voltage compensation for the pci express interface on the 41210 bridge. the nom inal compensation voltage is 0.5v. an external 24.9 1% pull-up resistor should be used to connect to vcc15. a single pull-up resistor can be used to for both of these signals. power plane maximum voltage plane current (amps) frequency (mhz) 133 100 66 number of slots 1 2 4 i vcc15 (core 1.5v) 1.68 1.61 1.55 i vcc15 (i/o 1.5v) 0.22 0.22 0.22 vccbgpe 0.005 0.005 0.005 i vccpe (pci express 1.5v) 0.70 0.70 0.70 i vcc33 (pci/pci-x mode 1 3.3v) 1 1. per pci-x bus segment 1.05 1.14 1.22 power plane thermal voltage plane current (amps) frequency (mhz) 133 100 66 number of slots 1 2 4 i vcc15 (core 1.5v) 1.24 1.18 1.11 i vcc15 (i/o 1.5v) 0.22 0.22 0.22 vccbgpe 0.005 0.005 0.005 i vccpe (pci express 1.5v) 0.69 0.69 0.69 i vcc33 (pci/pci-x mode 1 3.3v) 1 1. per pci-x bus segment 0.99 1.04 1.10
41210 bridge ? datasheet 38 ? rcomp is an analog pci interface compensation pin to the 41210 bridge. a 100 1% pull- down resistor should be used to connect the rcomp pin to ground. all three of these implementations are shown in figure 8 . figure 8. 41210 bridge reference and compensation circuit implementations 3.9 thermal specifications 3.9.1 power for tdp specifications, see 41210 bridge thermal specifications for the 41210 bridge component. fc-bga packages have poor heat transfer capability into the board and have minimal thermal capability without thermal solutions. intel recommends that system designers plan for a heatsink when using the 41210 bridge component. 3.9.2 die temperature to ensure proper operation and reliability of the 41210 bridge component, the die temperatures must be at or below the values specified in table 30 . system and/or component level thermal solutions are required to maintain die te mperatures below the maximum temperature specifications.
datasheet ? 41210 bridge 39 table 30. 41210 bridge thermal specifications note: mode 1: pci-x 66mhz, 64-bit, 4 slots/devices no connect: unused pci segment (no slots/devices on pci bus segment) 3.9.3 thermal solution component suppliers 3.9.3.1 torsional clip heatsink thermal solution note: the enabled components may not be currently available from all suppliers. contact the supplier directly to verify time of component availability. parameter maxinum t case 105c tdp mode#1/mode#1 8.70w tdp mode#1/no connect 8.30w tdp ddr/no connect 8.10w part intel part number supplier (part number) contact information heatsink assembly includes: unidirectional fin heatsink thermal interface material torsional clip c76435-001 cci/ack harry lin (usa) 714-739-5797 hlinack@aol.com monica chih (taiwan) 866-2-29952666, x131 monica_chih@ccic.com.tw unidirectional fin heatsink (31.0 x 31.0 x 12.2mm) c76434-001 cci/ack harry lin (usa) 714-739-5797 hlinack@aol.com monica chih (taiwan) 866-2-29952666, x131 monica_chih@ccic.com.tw thermal interface ( chomerics t-710) a69230-001 chomerics 69-12-22066-t710 todd sousa (usa) 360-606-8171 tsousa@parker.com heatsink attach clip c17725-001 cci/ack harry lin (usa) 714-739-5797 hlinack@aol.com monica chih (taiwan) 866-2-29952666, x131 monica_chih@ccic.com.tw solder-down anchor a13494-005 foxconn (hb96030-dw) julia jiang (usa) 408-919-6178 juliaj@foxconn.com
41210 bridge ? datasheet 40 package specification and ballout 4 4.1 package specification the 41210 bridge is in a 567-ball fcbga package, 31mm x 31mm in size, with a 1.27mm ball pitch (see figure 9 and figure 10 ). figure 9. 41210 bridge package dimensions (top view) pkg_567-ball _to p 0.550 in. handl i ng excl usi on area di e ar ea 17.00 mm 21.00 mm 31.00 mm 0.550 in. 17.00 mm 21.00 mm 31.00 mm
datasheet ? 41210 bridge 41 figure 10. 41210 bridge package dimensions (side view) note: primary datum -c- and seating plane are defined by the spherical crowns of the solder balls. note: all dimensions and tolerances conform to ansi y14.5m-1982
41210 bridge ? datasheet 42 4.2 ball map

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41210 bridge ? datasheet 44 4.3 signal list, sorted by ball location table 31. signal list, sorted by ball name (sheet 1 of 4) ball signal name ball signal name ball signal name a1 c1 b_intd# e1 b_nc4 a2 b_strap5 c2 vss e2 vss a3 reserved5 c3 b_test1 e3 b_nc9 a4 vss c4 nc4 e4 b_nc2 a5 nc2 c5 vss e5 vss a6 tdo c6 nc18 e6 b_strap4 a7 vcc33 c7 smbclk e7 tms a8 vss c8 vss e8 vss a9 petn[5] c9 pern[5] e9 tdi a10 petp[5] c10 pern[4] e10 vss a11 c11 perp[4] e11 petp[7] a12 c12 vccpe e12 pern[6] a13 vssbgpe c13 pern[2] e13 vss a14 vccpe c14 vccbgpe e14 pern[0] a15 pern[1] c15 vccpe e15 perp[0] a16 perp[1] c16 refclkp e16 pe_rcomp[0] a17 vss c17 refclkn e17 a_pcixcap a18 smbus[3] c18 a_strap0 e18 cfgrst# a19 b_strap0 c19 a_strap3 e19 nc6 a20 vss c20 vss e20 vss a21 a_strap4 c21 reserved1 e21 a_nc10 a22 nc3 c22 vcc33 e22 a_nc8 a23 a_nc2 c23 vss e23 vss a24 vss c24 a_intd# e24 vcc33 b1 b_nc7 d1 b_test2 f1 vcc33 b2 b_nc1 d2 b_nc3 f2 b_inta# b3 b_strap1 d3 b_nc6 f3 b_intc# b4 reserved6 d4 reserved7 f4 b_nc10 b5 b_strap6 d5 vcc33 f5 reserved8 b6 nc19 d6 nc5 f6 nc7 b7 tck d7 b_pcixcap f7 nc9 b8 cfgretry d8 smbdat f8 nc8 b9 perp[5] d9 petn[6] f9 trst# b10 vss d10 petp[6] f10 perp[7] b11 petn[4] d11 vss f11 petn[7] b12 petp[4] d12 perp[6] f12 vccpe b13 vss d13 perp[2] f13 petn[0] b14 petn[2] d14 vss f14 petp[0] b15 petp[2] d15 petn[1] f15 vss b16 vss d16 petp[1] f16 vssape b17 pe_rcomp[1] d17 vss f17 perst# b18 vcc33 d18 a_strap1 f18 nc1 b19 b_strap2 d19 a_strap5 f19 a_strap6 b20 smbus[2] d20 smbus[5] f20 reserved4 b21 reserved2 d21 reserved3 f21 a_nc9 b22 a_strap2 d22 a_nc6 f22 a_test1 b23 a_test2 d23 a_intc# f23 a_nc4 b24 a_nc1 d24 a_nc3 f24 a_intb#
datasheet ? 41210 bridge 45 ball signal name ball signal name ball signal name g1 b_intb# j1 vss l1 b_ad[41] g2 vss j2 b_ad[45] l2 b_ad[42] g3 b_nc5 j3 b_ad[46] l3 vcc15 g4 b_nc8 j4 vss l4 b_req0# g5 vss j5 b_gnt0# l5 b_ad[56] g6 b_cbe6# j6 b_ad[60] l6 vcc33 g7 b_cbe7# j7 b_ad[61] l7 b_ad[57] g8 vss j8 vccapci1 l8 b_gnt5# g9 b_cbe4# j9 vss l9 vss g10 pern[7] j10 vccpe l10 vcc15 g11 vss j11 vss l11 vss g12 pern[3] j12 vccpe l12 vcc15 g13 petp[3] j13 vss l13 vss g14 vss j14 vccpe l14 vcc15 g15 vccape j15 vss l15 vss g16 smbus[1] j16 vcc15 l16 vcc15 g17 vss j17 a_ad[63] l17 a_ad[59] g18 nc11 j18 a_cbe5# l18 vss g19 nc12 j19 vss l19 a_ad[58] g20 vss j20 a_par64 l20 a_ad[43] g21 a_nc5 j21 a_ad[47] l21 vss g22 a_nc7 j22 vss l22 a_req4# g23 vss j23 a_ad[46] l23 a_ad[42] g24 a_inta# j24 a_gnt1# l24 vss h1 b_ad[48] k1 b_gnt1# m1 h2 b_ad[49] k2 vss m2 b_ad[39] h3 vcc33 k3 b_ad[43] m3 b_ad[40] h4 b_ad[47] k4 b_ad[44] m4 vss h5 b_ad[62] k5 vss m5 b_ad[54] h6 vss k6 b_ad[58] m6 b_ad[55] h7 b_par64 k7 b_ad[59] m7 vss h8 b_ad[63] k8 vss m8 nc14 h9 b_cbe5# k9 vcc15 m9 vcc15 h10 vss k10 vss m10 vss h11 vccpe k11 vcc15 m11 vcc15 h12 perp[3] k12 vss m12 vss h13 petn[3] k13 vcc15 m13 vcc15 h14 vss k14 vss m14 vss h15 vccpe k15 vcc15 m15 vcc15 h16 rstin# k16 vss m16 vss h17 a_cbe4# k17 a_ad[61] m17 a_ad[57] h18 vcc33 k18 a_ad[60] m18 a_ad[56] h19 a_cbe6# k19 a_ad[62] m19 vcc33 h20 a_cbe7# k20 vss m20 nc15 h21 vcc33 k21 nc13 m21 a_ad[41] h22 a_ad[49] k22 a_ad[45] m22 vcc15 h23 a_ad[48] k23 vss m23 a_ad[40] h24 vcc33 k24 a_ad[44] m24 table 31. signal list, sorted by ball name (sheet 2 of 4)
41210 bridge ? datasheet 46 ball signal name ball signal name ball signal name n1 r1 vss u1 b_m66en n2 vss r2 b_ad[32] u2 b_perr# n3 b_ad[37] r3 b_ad[33] u3 vss n4 b_ad[38] r4 vss u4 b_frame# n5 vss r5 b_pme# u5 b_irdy# n6 b_ad[52] r6 nc16 u6 vss n7 b_ad[53] r7 vcc33 u7 b_clko[5] n8 b_rst# r8 vccapci2 u8 b_clko[6] n9 vss r9 vss u9 vcc33 n10 vcc15 r10 vcc15 u10 b_clkin n11 vss r11 vss u11 b_strap3 n12 vcc15 r12 vcc15 u12 vss n13 vss r13 vss u13 a_clkin n14 vcc15 r14 vcc15 u14 a_clko[4] n15 vss r15 vss u15 vss n16 vcc15 r16 vcc15 u16 a_clko[5] n17 a_ad[55] r17 vccapci3 u17 a_clko[3] n18 a_req3# r18 a_ad[51] u18 vss n19 a_ad[54] r19 vss u19 a_stop# n20 vss r20 a_ad[50] u20 a_devsel# n21 a_ad[39] r21 a_lock# u21 vss n22 a_ad[38] r22 vss u22 a_trdy# n23 vss r23 a_ad[35] u23 a_gnt5# n24 r24 a_ad[34] u24 vss p1 b_ad[34] t1 b_req3# v1 vss p2 b_133en t2 vss v2 b_serr# p3 vss t3 b_devsel# v3 b_stop# p4 b_ad[35] t4 nc10 v4 vcc33 p5 b_ad[36] t5 vcc33 v5 b_req4# p6 vss t6 b_req2# v6 b_clko[4] p7 b_ad[50] t7 b_clko[3] v7 vss p8 b_ad[51] t8 vss v8 b_clko[2] p9 vcc15 t9 vcc15 v9 b_clko[1] p10 vss t10 vss v10 vss p11 vcc15 t11 vcc15 v11 rcomp p12 vss t12 vss v12 vcc15 p13vcc15t13vcc15v13 vss p14 vss t14 vss v14 a_clko[0] p15 vcc15 t15 vcc15 v15 a_clko[6] p16 vss t16 vss v16 vcc15 p17 a_ad[53] t17 vcc33 v17 a_clko[2] p18 vss t18 a_m66en v18 a_req2# p19 a_ad[52] t19 a_serr# v19 vss p20 a_perr# t20 vcc33 v20 a_133en p21 vss t21 a_ad[33] v21 a_pme# p22 a_ad[37] t22 a_ad[32] v22 vss p23 a_ad[36] t23 vcc33 v23 a_frame# p24 vss t24 nc17 v24 a_irdy# table 31. signal list, sorted by ball name (sheet 3 of 4)
datasheet ? 41210 bridge 47 ball signal name ball signal name ball signal name w1 b_ad[16] aa1 vcc33 ac1 b_req64# w2 vcc33 aa2 b_ad[18] ac2 b_ad[0] w3 b_lock# aa3 b_ad[19] ac3 vcc15 w4 b_trdy# aa4 vss ac4 b_ad[4] w5 vss aa5 b_cbe3# ac5 b_ad[5] w6 b_ad[23] aa6 b_ad[24] ac6 vcc33 w7 b_ad[25] aa7 vss ac7 b_ad[9] w8 vss aa8 b_ad[28] ac8 b_cbe0# w9 b_ad[29] aa9 b_ad[31] ac9 vss w10 b_clko[0] aa10 vss ac10 b_ad[14] w11 vcc33 aa11 b_gnt3# ac11 b_par w12 b_gnt4# aa12 b_req5# ac12 vss w13 a_req5# aa13 vss ac13 a_ad[15] w14 vss aa14 a_gnt4# ac14 a_cbe1# w15 a_ad[30] aa15 a_ad[31] ac15 vss w16 a_clko[1] aa16 vss ac16 a_ad[11] w17 vss aa17 a_rst# ac17 a_ad[9] w18 a_ad[25] aa18 a_ad[26] ac18 vss w19 a_gnt0# aa19 vss ac19 a_ad[7] w20 vss aa20 a_cbe3# ac20 a_ad[5] w21 a_req0# aa21 a_ad[21] ac21 vss w22 a_req1# aa22 vss ac22 a_ad[2] w23 vss aa23 a_ad[18] ac23 a_ad[0] w24 a_ad[16] aa24 a_cbe2# ac24 a_req64# y1 b_cbe2# ab1 b_ack64# ad1 vss y2 b_ad[17] ab2 vss ad2 b_ad[1] y3 vss ab3 b_ad[20] ad3 b_ad[2] y4 b_ad[21] ab4 b_ad[3] ad4 vss y5 b_ad[22] ab5 vss ad5 b_ad[6] y6 vcc15 ab6 b_req1# ad6 b_ad[7] y7 b_ad[26] ab7 b_ad[8] ad7 vss y8 b_ad[27] ab8 vcc33 ad8 b_ad[10] y9 vcc33 ab9 b_ad[11] ad9 b_ad[12] y10 b_ad[30] ab10 b_ad[13] ad10 vss y11 b_gnt2# ab11 vss ad11 b_ad[15] y12 vss ab12 b_cbe1# ad12 y13 a_gnt3# ab13 a_par ad13 y14 a_gnt2# ab14 vcc33 ad14 a_ad[14] y15 vcc33 ab15 a_ad[12] ad15 a_ad[13] y16 a_ad[28] ab16 a_ad[29] ad16 vss y17 a_ad[27] ab17 vss ad17 a_ad[10] y18 vss ab18 a_ad[8] ad18 a_cbe0# y19 a_ad[23] ab19 a_ad[24] ad19 vcc33 y20 a_ad[22] ab20 vcc15 ad20 a_ad[6] y21 vcc33 ab21 a_ad[3] ad21 a_ad[4] y22 a_ad[19] ab22 a_ad[20] ad22 vss y23 a_ad[17] ab23 vss ad23 a_ad[1] y24 vcc33 ab24 a_ack64# ad24 vss table 31. signal list, sorted by ball name (sheet 4 of 4)
41210 bridge ? datasheet 48 4.4 signal list, sorted by signal name table 32. signal list, sorted by signal name (sheet 1 of 4) ball signal name ball signal name ball signal name v20 a_133en j23 a_ad[46] a23 a_nc2 ab24 a_ack64# j21 a_ad[47] d24 a_nc3 ac23 a_ad[0] h23 a_ad[48] f23 a_nc4 ad23 a_ad[1] h22 a_ad[49] g21 a_nc5 ac22 a_ad[2] r20 a_ad[50] d22 a_nc6 ab21 a_ad[3] r18 a_ad[51] g22 a_nc7 ad21 a_ad[4] p19 a_ad[52] e22 a_nc8 ac20 a_ad[5] p17 a_ad[53] f21 a_nc9 ad20 a_ad[6] n19 a_ad[54] e21 a_nc10 ac19 a_ad[7] n17 a_ad[55] r21 a_lock# ab18 a_ad[8] m18 a_ad[56] t18 a_m66en ac17 a_ad[9] m17 a_ad[57] ab13 a_par ad17 a_ad[10] l19 a_ad[58] j20 a_par64 ac16 a_ad[11] l17 a_ad[59] e17 a_pcixcap ab15 a_ad[12] k18 a_ad[60] p20 a_perr# ad15 a_ad[13] k17 a_ad[61] v21 a_pme# ad14 a_ad[14] k19 a_ad[62] w21 a_req0# ac13 a_ad[15] j17 a_ad[63] w22 a_req1# w24 a_ad[16] ad18 a_cbe0# v18 a_req2# y23 a_ad[17] ac14 a_cbe1# n18 a_req3# aa23 a_ad[18] aa24 a_cbe2# l22 a_req4# y22 a_ad[19] aa20 a_cbe3# w13 a_req5# ab22 a_ad[20] h17 a_cbe4# ac24 a_req64# aa21 a_ad[21] j18 a_cbe5# aa17 a_rst# y20 a_ad[22] h19 a_cbe6# t19 a_serr# y19 a_ad[23] h20 a_cbe7# u19 a_stop# ab19 a_ad[24] u13 a_clkin c18 a_strap0 w18 a_ad[25] v14 a_clko[0] d18 a_strap1 aa18 a_ad[26] w16 a_clko[1] b22 a_strap2 y17 a_ad[27] v17 a_clko[2] c19 a_strap3 y16 a_ad[28] u17 a_clko[3] a21 a_strap4 ab16 a_ad[29] u14 a_clko[4] d19 a_strap5 w15 a_ad[30] u16 a_clko[5] f19 a_strap6 aa15 a_ad[31] v15 a_clko[6] f22 a_test1 t22 a_ad[32] u20 a_devsel# b23 a_test2 t21 a_ad[33] v23 a_frame# u22 a_trdy# r24 a_ad[34] w19 a_gnt0# p2 b_133en r23 a_ad[35] j24 a_gnt1# ab1 b_ack64# p23 a_ad[36] y14 a_gnt2# ac2 b_ad[0] p22 a_ad[37] y13 a_gnt3# ad2 b_ad[1] n22 a_ad[38] aa14 a_gnt4# ad3 b_ad[2] n21 a_ad[39] u23 a_gnt5# ab4 b_ad[3] m23 a_ad[40] v24 a_irdy# ac4 b_ad[4] m21 a_ad[41] g24 a_inta# ac5 b_ad[5] l23 a_ad[42] f24 a_intb# ad5 b_ad[6] l20 a_ad[43] d23 a_intc# ad6 b_ad[7] k24 a_ad[44] c24 a_intd# ab7 b_ad[8] k22 a_ad[45] b24 a_nc1 ac7 b_ad[9]
datasheet ? 41210 bridge 49 ball signal name ball signal name ball signal name ad8 b_ad[10] k6 b_ad[58] h7 b_par64 ab9 b_ad[11] k7 b_ad[59] d7 b_pcixcap ad9 b_ad[12] j6 b_ad[60] u2 b_perr# ab10 b_ad[13] j7 b_ad[61] r5 b_pme# ac10 b_ad[14] h5 b_ad[62] l4 b_req0# ad11 b_ad[15] h8 b_ad[63] ab6 b_req1# w1 b_ad[16] ac8 b_cbe0# t6 b_req2# y2 b_ad[17] ab12 b_cbe1# t1 b_req3# aa2 b_ad[18] y1 b_cbe2# v5 b_req4# aa3 b_ad[19] aa5 b_cbe3# aa12 b_req5# ab3 b_ad[20] g9 b_cbe4# ac1 b_req64# y4 b_ad[21] h9 b_cbe5# n8 b_rst# y5 b_ad[22] g6 b_cbe6# v2 b_serr# w6 b_ad[23] g7 b_cbe7# v3 b_stop# aa6 b_ad[24] u10 b_clkin a19 b_strap0 w7 b_ad[25] w10 b_clko[0] b3 b_strap1 y7 b_ad[26] v9 b_clko[1] b19 b_strap2 y8 b_ad[27] v8 b_clko[2] u11 b_strap3 aa8 b_ad[28] t7 b_clko[3] e6 b_strap4 w9 b_ad[29] v6 b_clko[4] a2 b_strap5 y10 b_ad[30] u7 b_clko[5] b5 b_strap6 aa9 b_ad[31] u8 b_clko[6] c3 b_test1 r2 b_ad[32] t3 b_devsel# d1 b_test2 r3 b_ad[33] u4 b_frame# w4 b_trdy# p1 b_ad[34] j5 b_gnt0# b8 cfgretry p4 b_ad[35] k1 b_gnt1# e18 cfgrst# p5 b_ad[36] y11 b_gnt2# f18 nc1 n3 b_ad[37] aa11 b_gnt3# a5 nc2 n4 b_ad[38] w12 b_gnt4# a22 nc3 m2 b_ad[39] l8 b_gnt5# c4 nc4 m3 b_ad[40] u5 b_irdy# d6 nc5 l1 b_ad[41] f2 b_inta# e19 nc6 l2 b_ad[42] g1 b_intb# f6 nc7 k3 b_ad[43] f3 b_intc# f8 nc8 k4 b_ad[44] c1 b_intd# f7 nc9 j2 b_ad[45] b2 b_nc1 t4 nc10 j3 b_ad[46] e4 b_nc2 g18 nc11 h4 b_ad[47] d2 b_nc3 g19 nc12 h1 b_ad[48] e1 b_nc4 k21 nc13 h2 b_ad[49] g3 b_nc5 m8 nc14 p7 b_ad[50] d3 b_nc6 m20 nc15 p8 b_ad[51] b1 b_nc7 r6 nc16 n6 b_ad[52] g4 b_nc8 t24 nc17 n7 b_ad[53] e3 b_nc9 c6 nc18 m5 b_ad[54] f4 b_nc10 b6 nc19 m6 b_ad[55] w3 b_lock# e16 pe_rcomp[0] l5 b_ad[56] u1 b_m66en b17 pe_rcomp[1] l7 b_ad[57] ac11 b_par e14 pern[0] table 32. signal list, sorted by signal name (sheet 2 of 4)
41210 bridge ? datasheet 50 ball signal name ball signal name ball signal name a15 pern[1] a18 smbus[3] f1 vcc33 c13 pern[2] d20 smbus[5] h3 vcc33 g12 pern[3] b7 tck h18 vcc33 c10 pern[4] e9 tdi h21 vcc33 c9 pern[5] a6 tdo h24 vcc33 e12 pern[6] e7 tms l6 vcc33 g10 pern[7] f9 trst# m19 vcc33 e15 perp[0] j16 vcc15 r7 vcc33 a16 perp[1] k9 vcc15 t5 vcc33 d13 perp[2] k11 vcc15 t17 vcc33 h12 perp[3] k13 vcc15 t20 vcc33 c11 perp[4] k15 vcc15 t23 vcc33 b9 perp[5] l3 vcc15 u9 vcc33 d12 perp[6] l10 vcc15 v4 vcc33 f10 perp[7] l12 vcc15 w2 vcc33 f17 perst# l14 vcc15 w11 vcc33 f13 petn[0] l16 vcc15 y9 vcc33 d15 petn[1] m9 vcc15 y15 vcc33 b14 petn[2] m11 vcc15 y21 vcc33 h13 petn[3] m13 vcc15 y24 vcc33 b11 petn[4] m15 vcc15 aa1 vcc33 a9 petn[5] m22 vcc15 ab8 vcc33 d9 petn[6] n10 vcc15 ab14 vcc33 f11 petn[7] n12 vcc15 ac6 vcc33 f14 petp[0] n14 vcc15 ad19 vcc33 d16 petp[1] n16 vcc15 j8 vccapci1 b15 petp[2] p9 vcc15 r8 vccapci2 g13 petp[3] p11 vcc15 r17 vccapci3 b12 petp[4] p13 vcc15 g15 vccape a10 petp[5] p15 vcc15 c14 vccbgpe d10 petp[6] r10 vcc15 a14 vccpe e11 petp[7] r12 vcc15 c12 vccpe v11 rcomp r14 vcc15 c15 vccpe c17 refclkn r16 vcc15 f12 vccpe c16 refclkp t9 vcc15 h11 vccpe c21 reserved1 t11 vcc15 h15 vccpe b21 reserved2 t13 vcc15 j10 vccpe d21 reserved3 t15 vcc15 j12 vccpe f20 reserved4 v12 vcc15 j14 vccpe a3 reserved5 v16 vcc15 a4 vss b4 reserved6 y6 vcc15 a8 vss d4 reserved7 ab20 vcc15 a17 vss f5 reserved8 ac3 vcc15 a20 vss h16 rstin# a7 vcc33 a24 vss c7 smbclk b18 vcc33 b10 vss d8 smbdat c22 vcc33 b13 vss g16 smbus[1] d5 vcc33 b16 vss b20 smbus[2] e24 vcc33 c2 vss table 32. signal list, sorted by signal name (sheet 3 of 4)
datasheet ? 41210 bridge 51 ball signal name ball signal name ball signal name c5 vss l21 vss v10 vss c8 vss l24 vss v13 vss c20 vss m4 vss v19 vss c23 vss m7 vss v22 vss d11 vss m10 vss w5 vss d14 vss m12 vss w8 vss d17 vss m14 vss w14 vss e2 vss m16 vss w17 vss e5 vss n2 vss w20 vss e8 vss n5 vss w23 vss e10 vss n9 vss y3 vss e13 vss n11 vss y12 vss e20 vss n13 vss y18 vss e23 vss n15 vss aa4 vss f15 vss n20 vss aa7 vss g2 vss n23 vss aa10 vss g5 vss p3 vss aa13 vss g8 vss p6 vss aa16 vss g11 vss p10 vss aa19 vss g14 vss p12 vss aa22 vss g17 vss p14 vss ab2 vss g20 vss p16 vss ab5 vss g23 vss p18 vss ab11 vss h6 vss p21 vss ab17 vss h10 vss p24 vss ab23 vss h14 vss r1 vss ac9 vss j1 vss r4 vss ac12 vss j4 vss r9 vss ac15 vss j9 vss r11 vss ac18 vss j11 vss r13 vss ac21 vss j13 vss r15 vss ad1 vss j15 vss r19 vss ad4 vss j19 vss r22 vss ad7 vss j22 vss t2 vss ad10 vss k2 vss t8 vss ad16 vss k5 vss t10 vss ad22 vss k8 vss t12 vss ad24 vss k10 vss t14 vss f16 vssape k12 vss t16 vss a13 vssbgpe k14 vss u3 vss a1 k16 vss u6 vss a11 k20 vss u12 vss a12 k23 vss u15 vss m1 l9 vss u18 vss m24 l11 vss u21 vss n1 l13 vss u24 vss n24 l15 vss v1 vss ad12 l18 vss v7 vss ad13 table 32. signal list, sorted by signal name (sheet 4 of 4)
41210 bridge ? datasheet 52 this page intenti onally left blank.

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